With a development of display technology, display devices with a large size and a high resolution have become a trend.
Although liquid crystal display devices with a large size and a high resolution bring a superior visual experience when being used to display images, such display devices have a high power consumption, which may cause an increase of heat and a reduction of reliability. At present, the general resolution for sources to be displayed is at a level of high definition (HD), which corresponds to a resolution of 1280*720. Since the amount of the sources for high resolution display screens is very a few, it is required to perform an image processing procedure in a FPGA chip to match the resolution of the sources with the resolution of the display screen, in order to ensure a smooth output.
The power consumption of FPGA may include a statistic power consumption and a dynamic power consumption. The statistic power consumption is mainly caused by a leakage current of a transistor, in particular, including a leakage current from a source to a drain and a leakage current from a gate to a substrate base. The dynamic power consumption is mainly caused by the charging and discharging of a capacitor, in which the main influencing parameters are voltage, node capacitance and operating frequency. In a design for a traditional liquid crystal display device, the dynamic power consumption occupies 90% of the total power consumption or more. Accordingly, the reduction of dynamic power consumption is essential for the reduction of the total power consumption.
Generally, the problem related to the power consumption of the display device is solved by chip design. In other words, the problem related to the power consumption of the display device is usually solved by designing an intelligent chip and replacing the high power consumption chip with the intelligent chip. However, this may increase the costs for manufacturing the liquid crystal display device.